1. Field of the Invention
The present invention relates to the field of data transfer. More particularly, the present invention relates to an apparatus and method for arbitrating bus ownership of a plurality of communications buses and for efficiently performing data transfers, without processor assistance, between a first component coupled to one communication bus and a second component coupled to another communication bus.
2. Background Art Relating to the Present Invention
It is commonly known that a computer system comprises a number of electronic components which transfer data in order to accomplish a specific task. One well-known method of data transfer is direct memory access ("DMA transfer") which is usually performed by a DMA element. As shown in FIG. 1, a conventional computer system 10 supporting DMA transfers comprises a DMA element 20, main memory element 40 and a plurality of bus masters coupled together through a single communication bus 30 (e.g., a system bus). A "bus master" is an element, component or device which can initiate sequences through a communication bus to perform various operations. In FIG. 1, for example, a host processor 50 and a peripheral device 60 having internal memory 70 are bus masters.
The host processor 50 initiates a DMA transfer, for example a DMA transfer between the main memory element 40 and the internal memory 70 of the peripheral device 60, by transmitting certain information to the DMA element 20 through the communication bus 30. Such information may include the amount of data to be transferred, the starting address of the memory block storing the data, the type of data transfer and the like. The DMA element 20 starts and continues to transfer data between a main memory element 40 and the internal memory 70 until the DMA transfer is completed.
Recently, it is becoming desirous to employ multiple processors within a computer system in order to enhance its overall processing speed. Generally, these multi-processor computer systems comprise a host processor coupled to a first communication bus and any number of auxiliary processors coupled to a second communication bus. While multi-processor computer systems may provide greater processing speed, they afford a number of disadvantages. One such disadvantage is that in a multi-processor computer system, conventional DMA elements can not support DMA transfers between elements coupled to different communication buses. Additionally, initiating data transfers is restricted to only the host processor with no initiating transfer provisions available to the auxiliary processors residing on the second communication bus.
Besides these above-identified disadvantages, a number of performance disadvantages are also inherent with conventional DMA elements. One primary disadvantage is that conventional DMA elements perform DMA transfers through two sequential memory sequences (i.e., a memory read sequence followed by a memory write sequence). Thus, the time required to complete this DMA transfer is substantially greater than the DMA transfer performed through concurrent memory sequences.
A second disadvantage is that conventional DMA elements may not be interrupted or temporarily halted until the DMA transfer is complete. This prevents any processor from accessing the communication buses during a DMA transfer. For multi-processor computer systems executing real-time applications, this inability to interrupt or temporarily halt the DMA transfer may accidentally cause an application to "time-out" (e.g., a modem application terminating its connection) and at least precludes the computer system from achieving its optimal processing speed.
Another disadvantage is related to software overhead required by the host processor to service auxiliary processor interrupts signaling the need for data which would be delivered via a DMA transfer initiated by the host processor. Software overhead is a processor executed control operation requiring the host processor to (i) save to memory its current state before initiating the DMA transfer and (ii) restore this saved state after the data transfer has completed so that the processor may continue its pre-data transfer operations. As a result, the DMA transfer tends to be inefficient if the time required to perform the software overhead is relatively large compared to the time actually required by the DMA transfers.
Hence, it would be desirable too employ an apparatus that overcomes one or more of the cited disadvantages.
Another object of the present invention is to provide an apparatus and method for which simulates the operations of the host processor so that DMA transfers performed by the apparatus are transparent to other components coupled to the first communication bus to facilitate normal operations by the computer system under a DMA transfer.
Another object of the present invention is to provide an apparatus and method for enabling the host processor to access the second communication bus as a bus master.
A further object of the present invention is to provide an apparatus and method for interrupting or temporary halting DMA transfers by any processor in order to allow time critical execution of real-time applications without having to wait for a transfer to complete.
Yet another object of the present invention is to provide an apparatus and method for enabling processors on the second communication bus, in addition to the host processor, to initiate DMA transfers.